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Path: ~//proc/self/root/usr/lib/modules/5.4.0-216-generic/build/arch/x86/include/asm/

File Content: barrier.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_BARRIER_H
#define _ASM_X86_BARRIER_H

#include <asm/alternative.h>
#include <asm/nops.h>

/*
 * Force strict CPU ordering.
 * And yes, this might be required on UP too when we're talking
 * to devices.
 */

#ifdef CONFIG_X86_32
#define mb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "mfence", \
				      X86_FEATURE_XMM2) ::: "memory", "cc")
#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "lfence", \
				       X86_FEATURE_XMM2) ::: "memory", "cc")
#define wmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "sfence", \
				       X86_FEATURE_XMM2) ::: "memory", "cc")
#else
#define mb() 	asm volatile("mfence":::"memory")
#define rmb()	asm volatile("lfence":::"memory")
#define wmb()	asm volatile("sfence" ::: "memory")
#endif

/**
 * array_index_mask_nospec() - generate a mask that is ~0UL when the
 * 	bounds check succeeds and 0 otherwise
 * @index: array element index
 * @size: number of elements in array
 *
 * Returns:
 *     0 - (index < size)
 */
static inline unsigned long array_index_mask_nospec(unsigned long index,
		unsigned long size)
{
	unsigned long mask;

asm volatile ("cmp %1,%2; sbb %0,%0;"
			:"=r" (mask)
			:"g"(size),"r" (index)
			:"cc");
	return mask;
}

/* Override the default implementation from linux/nospec.h. */
#define array_index_mask_nospec array_index_mask_nospec

/* Prevent speculative execution past this barrier. */
#define barrier_nospec() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC)

#define dma_rmb()	barrier()
#define dma_wmb()	barrier()

#ifdef CONFIG_X86_32
#define __smp_mb()	asm volatile("lock; addl $0,-4(%%esp)" ::: "memory", "cc")
#else
#define __smp_mb()	asm volatile("lock; addl $0,-4(%%rsp)" ::: "memory", "cc")
#endif
#define __smp_rmb()	dma_rmb()
#define __smp_wmb()	barrier()
#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)

#define __smp_store_release(p, v)					\
do {									\
	compiletime_assert_atomic_type(*p);				\
	barrier();							\
	WRITE_ONCE(*p, v);						\
} while (0)

#define __smp_load_acquire(p)						\
({									\
	typeof(*p) ___p1 = READ_ONCE(*p);				\
	compiletime_assert_atomic_type(*p);				\
	barrier();							\
	___p1;								\
})

/* Atomic operations are already serializing on x86 */
#define __smp_mb__before_atomic()	do { } while (0)
#define __smp_mb__after_atomic()	do { } while (0)

#include <asm-generic/barrier.h>

/*
 * Make previous memory operations globally visible before
 * a WRMSR.
 *
 * MFENCE makes writes visible, but only affects load/store
 * instructions.  WRMSR is unfortunately not a load/store
 * instruction and is unaffected by MFENCE.  The LFENCE ensures
 * that the WRMSR is not reordered.
 *
 * Most WRMSRs are full serializing instructions themselves and
 * do not require this barrier.  This is only required for the
 * IA32_TSC_DEADLINE and X2APIC MSRs.
 */
static inline void weak_wrmsr_fence(void)
{
	asm volatile("mfence; lfence" : : : "memory");
}

#endif /* _ASM_X86_BARRIER_H */

FILE FOLDER INFO

Name	Size	Permission
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e820	---	0755
fpu	---	0755
numachip	---	0755
trace	---	0755
uv	---	0755
vdso	---	0755
xen	---	0755
Kbuild	351 bytes	0644
acenv.h	1450 bytes	0644
acpi.h	4654 bytes	0644
acrn.h	310 bytes	0644
agp.h	1070 bytes	0644
alternative-asm.h	2725 bytes	0644
alternative.h	9789 bytes	0644
amd_nb.h	3166 bytes	0644
apb_timer.h	1301 bytes	0644
apic.h	14030 bytes	0644
apicdef.h	11534 bytes	0644
apm.h	1842 bytes	0644
arch_hweight.h	1083 bytes	0644
archrandom.h	2482 bytes	0644
asm-offsets.h	35 bytes	0644
asm-prototypes.h	924 bytes	0644
asm.h	4683 bytes	0644
atomic.h	6316 bytes	0644
atomic64_32.h	7873 bytes	0644
atomic64_64.h	5909 bytes	0644
barrier.h	3033 bytes	0644
bios_ebda.h	914 bytes	0644
bitops.h	10045 bytes	0644
boot.h	1563 bytes	0644
bootparam_utils.h	2866 bytes	0644
bug.h	2129 bytes	0644
bugs.h	502 bytes	0644
cache.h	641 bytes	0644
cacheflush.h	306 bytes	0644
cacheinfo.h	263 bytes	0644
calgary.h	1703 bytes	0644
ce4100.h	121 bytes	0644
checksum.h	133 bytes	0644
checksum_32.h	4964 bytes	0644
checksum_64.h	5541 bytes	0644
clocksource.h	488 bytes	0644
cmdline.h	302 bytes	0644
cmpxchg.h	7934 bytes	0644
cmpxchg_32.h	3247 bytes	0644
cmpxchg_64.h	561 bytes	0644
compat.h	5340 bytes	0644
cpu.h	975 bytes	0644
cpu_device_id.h	7496 bytes	0644
cpu_entry_area.h	4029 bytes	0644
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cpufeatures.h	28555 bytes	0644
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crash.h	488 bytes	0644
current.h	443 bytes	0644
debugreg.h	2631 bytes	0644
delay.h	208 bytes	0644
desc.h	11703 bytes	0644
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device.h	615 bytes	0644
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div64.h	2057 bytes	0644
dma-direct.h	333 bytes	0644
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dma.h	9811 bytes	0644
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hyperv-tlfs.h	25469 bytes	0644
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intel-family.h	4840 bytes	0644
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irqdomain.h	1644 bytes	0644
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kdebug.h	964 bytes	0644
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kmap_types.h	289 bytes	0644
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linkage.h	718 bytes	0644
livepatch.h	439 bytes	0644
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mach_traps.h	1013 bytes	0644
math_emu.h	395 bytes	0644
mc146818rtc.h	2835 bytes	0644
mce.h	12561 bytes	0644
mcsafe_test.h	1418 bytes	0644
mem_encrypt.h	3092 bytes	0644
microcode.h	3961 bytes	0644
microcode_amd.h	1573 bytes	0644
microcode_intel.h	2521 bytes	0644
misc.h	143 bytes	0644
mmconfig.h	374 bytes	0644
mmu.h	1662 bytes	0644
mmu_context.h	12354 bytes	0644
mmx.h	337 bytes	0644
mmzone.h	129 bytes	0644
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mmzone_64.h	430 bytes	0644
module.h	2096 bytes	0644
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mpx.h	3125 bytes	0644
mshyperv.h	7724 bytes	0644
msi.h	392 bytes	0644
msidef.h	1814 bytes	0644
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msr-trace.h	1387 bytes	0644
msr.h	11700 bytes	0644
mtrr.h	4730 bytes	0644
mwait.h	3826 bytes	0644
nmi.h	1426 bytes	0644
nops.h	4412 bytes	0644
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numa.h	1993 bytes	0644
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pci.h	3581 bytes	0644
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pgtable_64_types.h	4259 bytes	0644
pgtable_types.h	17079 bytes	0644
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rio.h	2630 bytes	0644
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